1. Field of the Invention
The present invention relates to the formation of integrated circuits, and, more particularly, to the formation of sidewall spacers in field effect transistors.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements such as, e.g., transistors, capacitors and resistors. These elements are connected internally to form complex circuits such as memory devices, logic devices and microprocessors. The performance of integrated circuits can be improved by increasing the number of functional elements per circuit in order to increase their functionality and/or by increasing the speed of operation of the circuit elements. A reduction of feature sizes allows the formation of a greater number of circuit elements on the same area, hence allowing an extension of the functionality of the circuit, and also reduces signal propagation delays, thus making an increase of the speed of operation of circuit elements possible.
Field effect transistors are used as switching elements in integrated circuits. They allow control of a current flowing through a channel region located between a source and a drain. The source and the drain are highly doped. In N-type transistors, the source and the drain are doped with an N-type dopant. Conversely, in P-type transistors, the source and the drain are doped with a P-type dopant. The doping of the channel region is inverse to the doping of the source and the drain. The conductivity of the channel region is controlled by a gate voltage applied to a gate electrode formed above the channel region and separated there-from by a thin insulating layer. Depending on the gate voltage, the channel region may be switched between a conductive “on” state and a substantially non-conductive “off” state.
Reducing the size of a field effect transistor may entail a reduction of the distance between the source and the drain, which is commonly denoted as “channel length.” A reduction of the channel length entails a plurality of issues associated therewith. First, advanced techniques of photolithography and etching have to be provided in order to reliably and reproducibly create transistors having short channel lengths. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the source and in the drain in order to provide a low sheet resistivity and a low contact resistivity in combination with a desired channel controllability.
When the integrated circuit is exposed to elevated temperature in stages of the manufacturing process after the formation of the source and the drain, P-type dopants and N-type dopants may diffuse at different speed. For example, boron which is used as a P-type dopant diffuses more quickly than the frequently used N-type dopant arsenic. Due to dopant diffusion, an initially provided dopant profile can be blurred. In order to at least partially compensate for the effects of dopant diffusion, different dopant profiles may be provided in N-type transistors and P-type transistors.
A method of forming a semiconductor structure 100 according to the state of the art will now be described with reference to FIGS. 1a-1c. A substrate 101 is provided. In the substrate 101, shallow trench isolations 102, 103, 104 and active regions 105, 106 of a first transistor element 150 and a second transistor element 160 are formed. Then, gate electrodes 107 and 109 which are separated from the substrate 101 by gate insulation layers 108 and 110, respectively, are formed over the substrate 101. This can be done by means of known advanced techniques of ion implantation, oxidation, deposition and photolithography.
Then, offset spacers 119, 120 are formed adjacent the gate electrode 107 of the first transistor element 150. Adjacent the gate electrode 109 of the second transistor element 160, offset spacers 121, 122 are formed. The formation of the offset spacers 119-122 may be performed by means of known methods comprising a conformal deposition of a layer of a material and an anisotropic etching of the layer. Subsequently, one or more extension implant processes are performed to form extended source regions 113, 117, and extended drain regions 114, 118 are formed at the gate electrodes 107, 109, adjacent the offset spacers 119, 120, 121, 122. This may be done by means of ion implantation.
The first transistor element 150 is an N-type transistor, and the second transistor element 160 is a P-type transistor. In each of the ion implantation processes performed in the formation of the active regions 105, 106 and the extended source and drain regions, one of the transistor elements 150, 160 is covered by a first mask. Then, the semiconductor structure 100 is irradiated with ions of a first dopant. Subsequently, the first mask is removed, the other transistor element is covered by a second mask and the semiconductor structure 100 is irradiated with ions of a second dopant. Thus, a P-type dopant may be introduced into the active region 105 of the first transistor element 150 and the extended source and drain regions of the second transistor element 160, and an N-type dopant can be introduced into the active region 106 of the second transistor element 160 and the extended source and drain regions of the first transistor element 150.
A first liner layer 123 is deposited on the semiconductor structure 100. Then, inner sidewall spacers 125, 126 are formed at the gate electrode 107 of the first transistor element 150. Similarly, inner sidewall spacers 127, 128 are formed at the gate electrode 109 of the second transistor element. Subsequently, a second liner layer 129 is deposited over the substrate 101 and outer sidewall spacers 130, 131, 132, 133 are formed at the gate electrodes 107, 109. The inner and the outer sidewall spacers may be formed by means of known methods comprising a conformal deposition of a material layer over the semiconductor structure 100 and an anisotropic etching of the material layer.
The liner layers 123, 129 are formed of a material having a significantly lower etch rate than the material of the inner sidewall spacers 125-128 and the outer sidewall spacers 130-133 when exposed to the etchant used in the etching processes applied in the formation of the sidewall spacers. Hence, the liner layers 123, 129 function as etch stop layers. In the formation of the inner sidewall spacers 125-128, the first liner layer 123 protects the subjacent portions of the semiconductor structure 100 from being affected by the etchant. In the formation of the outer sidewall spacers, the second liner layer 129 protects the portions of the semiconductor structure 100 located thereunder. The liner layers 123, 129, however, are affected by the etchants. Therefore, a thickness of the first liner layer 123 and the second liner layer 129 is reduced in the formation of the inner sidewall spacers 125-128 and the outer sidewall spacers 130-133, respectively.
A further stage of the manufacturing process is shown in FIG. 1b. The outer sidewall spacers 130, 131 of the first transistor element 150 are removed. This can be done by covering the second transistor element 160 by a mask (not shown) and exposing the semiconductor structure 100 to an etchant adapted to selectively remove a material of the outer sidewall spacers 130, 131. In this etching process, the second liner layer 129 is used as an etch stop layer. Since, however, the second liner layer 129 has already been affected by the etchant used in the formation of the outer sidewall spacers 130-133, the second liner layer 129 may be insufficient to protect the semiconductor structure 100. Hence, the etchant may affect the active region 105 and the gate electrode 107, which can lead to the formation of pits 134, 135, 136.
Yet another stage of the manufacturing process is shown in FIG. 1c. In the first transistor element 150, a source region 143 and a drain region 144 are formed. This may be done by implanting ions of an N-type dopant into the active region 105. A mask (not shown) is formed to protect the second transistor element 160 from an irradiation with ions. In the ion implantation, the offset spacers 119, 120 and the inner sidewall spacers 125, 126 protect subjacent portions of the active regions 105, 106 from being irradiated with ions. Therefore, the source region 143 and the drain region 144 are spaced apart from the gate electrode 107 by a distance which is determined by the thickness of the offset spacers 119, 120 and the inner sidewall spacers 125, 126. The source region 143 and the extended source region 113 together form a source of the first transistor element 150. A drain of the first transistor element 150 is provided by the drain region 144 and the extended drain region 114.
A further ion implantation is performed to form a source region 145 and a drain region 146 in the second transistor element 160. To prevent an irradiation of the first transistor element 150 with ions, a mask is formed over the first transistor element 150. The offset spacers 121, 122, the inner sidewall spacers 127, 128 and the outer sidewall spacers 132, 133 absorb ions impinging on the semiconductor structure 100. Thus, the source region 145 and the drain region 146 are spaced apart from the gate electrode 109 by a distance determined by the thickness of the outer sidewall spacers 132, 133 in addition to the thickness of the offset spacers 121, 122 and the inner sidewall spacers 127, 128. Hence, the spacing between the source region 145 and the drain region 146, respectively, and the gate electrode 109 is greater than the spacing between the source region 143 and the drain region 144, respectively, and the gate electrode 107 of the first transistor element 150. The source region 145 and the extended source region 117 together provide a source of the second transistor element. A drain of the second transistor element 160 is formed by the drain region 146 and the extended drain region 118.
If the semiconductor structure 100 is exposed to an elevated temperature in later phases of the manufacturing process, a diffusion of the dopants introduced into the source regions 143, 145 and the drain regions 144, 146 may occur. The P-type dopant in the source region 145 and the drain region 146 of the second transistor element 160 may diffuse more quickly than the N-type dopant in the source region 143 and the drain region 144 of the first transistor element 150. In particular, the P-type dopant may diffuse towards the gate electrode 109. The greater spacing between the source and drain regions and the gate electrode 109 in the second transistor element 160 insures that a sufficient distance between the dopants in the source and drain regions and the channel region below the gate electrode 109 can be maintained in spite of the dopant diffusion.
Finally, after a removal of the first liner layer 123 and the second liner layer 129, silicide regions 137, 138, 139, 140, 141, 142 are formed in the sources, the drains and the gate electrodes 107, 109 of the transistor elements 150, 160 in order to increase the conductivity of these features. As is well known to persons skilled in the art, the silicide regions 137-142 may be formed by depositing a refractory metal layer on the semiconductor structure and performing an annealing in order to initiate a chemical reaction between the refractory metal and the subjacent silicon. Since the offset spacers 119-122, the inner sidewall spacers 125-128 and the outer sidewall spacers 132, 133 prevent a contact between the refractory metal layer and portions of the substrate 101 close to the gate electrodes 107, 109, the silicide regions 137, 139, 140, 142 are spaced apart from the gate electrodes 107, 109.
A problem of the above-described method according to the state of the art is that, in features of the transistor elements 150, 160, an undesirable pitting may occur while the outer sidewall spacers 130, 131 of the first transistor element 150 are removed, as described above. This may impose constraints on yield and reliability of the manufacturing process.
Another problem of the above-described method according to the state of the art is that the spacing between the silicide regions 140, 142 formed adjacent the gate electrode 109 of the second transistor element 160 is greater than the spacing between the silicide regions 137, 139 adjacent the gate electrode 107 of the first transistor element 150. Hence, the electrical resistivity of the source and drain of the second transistor element 160 is greater than the electrical resistivity of the source and drain of the first transistor element 150. This may lead to undesirable signal propagation delays imposing constraints on the speed of operation of the second transistor element 160.
In view of the above problems, a need exists for a method of forming a semiconductor structure allowing the formation of different dopant profiles in transistor elements with reduced constraints on yield, reliability and/or speed of operation of the transistor elements.